Three-dimensional vertical NAND strings having one bit per cell are disclosed in an article by T. Endoh et al., titled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proc. (2001) 33-36. The charge states of a group of memory cells at each selected word-line-level is read by discharging (which is also referred to as “precharging”) the bit lines, providing suitable electrical biases to the bit lines such that the voltage at each bit line is determined by the charge states of the group of memory cells at the selected word-line-level, and sensing the voltages at the bit lines. A significant fraction of the total sense time is determined by the discharge time, i.e., the time it takes to reset the charge states of the bit lines by draining residual electrical charges generated by a previous sensing cycle. A faster discharge time can accelerate the operation of a three-dimensional memory device employing vertical NAND strings.